This invention relates to a sampling circuit for producing an output signal representative of a particular sample of a binary signal.
A circuit arrangement of this kind is used, for example, in an interface circuit which receives a digital signal. The interface circuit performs an adaptation to the clock frequency of a subsequent circuit. The state of the digital signal is then stored in a bistable element or latch. The input stage of such a bistable element comprises, for example, complementary transistors (for example, CMOS inverters). The digital signal is sampled each time in response to the occurrence of an edge of a clock signal applied to the circuit arrangement. The clock signal (the sampling signal) and the digital signal (the signal to be sampled) should have the same nominally frequency, but may exhibit a very small frequency deviation which usually changes also when viewed over a prolonged period of time.
When the digital signal is sampled during the transition of the signal level, undefined and metastable states may occur in the bistable element. During a metastable state, the signal level is not unambiguously "0" or "1".
In order to avoid a metastable state in the input stage of a bistable element, provisions are known from, for example, the publication "Control metastability in high-speed CMOS circuits" by T. Bowns, Electronic Design, 26.09.1991, pp. 74 to 80, notably page 78, left-hand column, third paragraph, which describes the series connection of two or three bistable elements. This is referred to as multi-stage synchronization. When the first bistable element enters a metastable state, such a state will probably disappear before the next bistable element is clocked.
It is an object of the invention to provide a circuit arrangement of the kind set forth which avoids the effects of metastable states in a bistable element.